The present invention relates to a clock signal control system.
It is a common practice with a semiconductor integrated circuit (LSI hereinafter) using a clock control system to locate a clock stop signal generating circuit at a single position. The clock stop signal generating circuit generates a clock stop signal for interrupting a clock signal while monitoring the computation information of various element units. Japanese Patent Laid-Open Publication No. 2-136966, for example, discloses a clock stop control system in which a clock stop signal generating circuit (CKSTPC) dealing with all the element units is built in an element unit referred to as a vector command executing section (VU-I).
However, the conventional clock signal control system is disadvantageous in that the clock stop signal generating circuit becomes complicated due to the increasing complication of the LSI. Specifically, the conventional clock signal control system has the following problems left unsolved.
(1) A first problem is that the system needs a number of design steps. Element units included in an LSI are sometimes designed by different designers. In the conventional LSI having the stop signal generating circuit implemented as a single unit, the designer of the stop signal generating circuit must grasp the stop timings of all the element units. Particularly, when the individual element unit ends processing at a timing dependent on data input to the element unit, a long verifying time is necessary for the clock stop signal generating circuit to be designed.
(2) A second problem is that a hierarchical structure is difficult to implement. In the conventional LSI, stop signals are generated by using a signal output from a single stop signal generating circuit implemented as a unit. When the number of element unit layers or the number of element units is increased, it is extremely difficult for the designer of the stop signal generating circuit to grasp the stop timings of all the element units.
(3) A third problem is that the stop signal generating circuit needs a broad area. Because the stop signal generating circuit of the conventional LSI is located outside of the element units, the stop signals cannot be generated by using signals appearing within the element units. As a result, the stop signal generating circuit is scaled up.
(4) A fourth problem is that the stop signal generating circuit with such a broad area consumes much power.
(5) A fifth problem is that the circuit arrangement is complicated. Specifically, in the conventional LSI, an element unit for stopping a clock signal and an element unit for generating a stop signal are separate from each other. Therefore, signals must be connected from the unit for stopping a clock signal to a unit including the stop signal generating circuit.